Manufacturing methods for integrated circuits have kept apace of, and in many cases enable, developments in the integrated circuits themselves. The ever smaller feature architecture within IC's has been accompanied by the technology that allows ever smaller packaging of the IC chips. Size, time and cost of IC production have all continued to shrink at tremendous rates.
Testing techniques associated with the various stages of IC packaging has been pressed to keep up with developments in the other areas of production. As new methods of connecting IC's into the surrounding electronic world have emerged, some older testing regimens have been a restriction on some developments.
Among the many packaging techniques that has emerged in recent years is the ball grid array (BGA). An improvement on earlier surface mount technology, BGA has allowed orders of magnitude improvements in speed, miniaturization and reliability of packaged IC's.
In BGA packaging, the array of solder pads that lends the name to the technique are typically mounted on one surface of a tiny printed circuit board (PCB), not much larger than the IC die itself, and made of a very thin substrate. The IC die is bonded and wired to connections on the opposite side of the small PCB using microscopic connections.
Typically, the small BGA PCB's are constructed in relatively large, array molded, laminate substrate sheets. By obviating the need for the long lead fingers of the prior lead frame array associated with previous surface mount technology, BGA packaging allows relatively dense arrays of units in process. The IC's are each bonded to the appropriate positions on the laminate substrate while the small BGA PCB's are still attached to each other. After bonding the dies to the substrate traces and testing the connections, the sheets are generally separated into individual units for functional testing.
Commonly, in this process in which multiple BGA units occupy the same laminate substrate strip, the individual traces on each of the units are connected to a common bus line (109, FIG. 1A) in order to allow an electrolytic plating process for Gold/Nickel plating, in an electro-plated substrate. These bus lines are eventually connected to the mold gate. This is called a “standard bus design” type packaging substrate.
During wire-bonding of such substrates, wire non-stick-on-pad (NSOP) and non-stick-on-lead (NSOL) conditions can be detected to avoid wire bond failures in assembly. This is done by using the electrical circuit as shown in conventional art FIG. 1A. The bus enabled circuit is formed after bonding IC 102 to BGA substrate 101 and wire-bonding first wire connection 106. The circuit closure is made through the gold wire in the spool, 105, the wire on the bond pad 106, to the lead finger 107 using the first wirebond 108, to bus-line 109 from lead fingers and finally to the mold gate 110.
The mold gate is grounded to the wire bond clamp. Using this circuit, if there is a bad bond on either the bond pad or lead finger, the circuit is affected, and the bond's quality can be easily measured electrically. Similar technology is used in leadframe based assembly, where the die attach pad is grounded to the wire bond clamp, through the leadframe, and is used for Non stick detection (NSD).
Since all the individual IC dies in a standard bus design substrate are connected electrically to each other via the bus lines, they cannot be tested, or burnt-in, in strip form and must be separated before being handled and tested as individual units. Also, since the first circuit is not completed until the first bond is completed on both ball pad side and lead finger side, the first ball bond NSOP detection has to be skipped in the wire-bond test step. For all successive bonds, this first bond serves as the electrical connection between the silicon and the lead fingers for grounding to the mold gate. If a no-bus type substrate design is used, in order to allow for in-strip testing, there is no NSO capability since the electrical circuit is not completed back to the mold gate in the absence of the bus-line connection. Conventional Art FIG. 1B illustrates a no-bus design. Lead fingers 107 are isolated from each other and from mold gate grounding 110. The result is an open circuit 105 and an inability to check for proper sticking in connection wire 106.
The current art, then, is disadvantageous because the prevalent and method of NSD requires that lead fingers be grounded which prohibits in-strip functional testing and burn-in of the packaged ICs.